1. Field of the Invention
This invention relates generally to semiconductor memory devices, and more particularly to a boost voltage generator for controlling a memory cell array.
2. Description of the Related Art
FIG. 1 is a diagram showing the general structure of a semiconductor memory device. As shown in FIG. 1, the memory device includes a plurality of memory cell array blocks 10. Each cell array block has an associated row decoder 12 for selecting a word line and column decoder 14 for selecting a bit line so as to select a memory cell within the cell array block. The memory device also includes a peripheral circuit portion 16 for controlling the operation of an internal signal.
The external power supply voltage applied to the semiconductor memory device is divided into a peripheral reference voltage signal (VREFP) which is an internal power supply signal that is applied to the peripheral circuit. The external power supply is also divided into an array reference voltage signal (VREFA) which is an internal power supply signal that is applied to the memory array circuit. The voltage level of each internal power supply is adjusted as needed. The voltage levels of these two internal power supply signals is maintained at a constant level in certain areas of the integrated circuit by maintaining the external power supply signal (VCC) at a constant level.
However, the voltage levels required for the two internal power supply signals might be different for different circumstances. For example, since the speed of the semiconductor memory device is related to the voltage level of the VREFP signal which is applied to the peripheral circuit, it is advantageous to increase the level of the VREFP signal as long as the power supply current remains within an acceptable level. Also, the current consumed by the semiconductor memory device is related to the voltage level of the VREFA signal which is applied to the memory cell array, and thus, it is advantageous to reduce the voltage level of the VREFA signal as low as possible.
FIG. 2 is a block diagram of a prior art boost voltage generator which generates a boosted power supply voltage signal (VPP). The circuit of FIG. 2 includes a level detecting portion 20, a pulse generating portion 22 and a pumping portion 24. The boosted power supply voltage signal VPP is generated from the VREFP signal (which is applied to the peripheral circuit) and controls the word lines of the semiconductor memory cell arrays.
Referring to FIG. 2, after the VREFP signal is applied to the peripheral circuit, the pulse generating portion 22 and the pumping portion 24 continuously operate to generate the boosted power supply voltage signal VPP at a predetermined voltage level. When the voltage level of the boosted signal VPP reaches the predetermined level, the level detecting portion 20 stops the operation of the pulse generating portion 22. Thus, the pumping portion 24 stops operating as well.
The level detecting portion 20 receives the boosted power supply voltage signal VPP and outputs an oscillating boosted power voltage signal (VPPOSCE). The pulse generating portion 22 generates a boosted power driving voltage signal (VPPDRV) responsive to the VPPOSCE signal. The pumping portion 24 receives the VPPDRV signal from the pulse generating portion 22 and continuously performs the pumping operation until the boosted power voltage signal VPP reaches a predetermined level. Thus, the boosted power voltage signal VPP, which is generating according to the process described above, controls the word lines of the semiconductor memory cell arrays, thereby controlling the memory cells. FIG. 3 is a schematic diagram of a prior art memory cell having a cell transistor in a general semiconductor memory device.
Referring to FIG. 3, the boosted power voltage signal VPP for controlling the cell transistor 30, which is connected to a word line W/L, should be maintained at a voltage level corresponding to the sum of the VREFP signal, a threshold voltage (VT) of the cell, and a predetermined margin voltage so that an adequate read/write operation can be performed through a full active RESTORE operation.
FIG. 4 is a schematic diagram showing the detailed structure of the level detecting portion 20 of the boost voltage generating circuit shown in FIG. 2. The signal VREFP is provided to the level detecting circuit shown in FIG. 4 and the signal VPPOSCE is output therefrom.
In the prior art level detector, the internal boosted power supply signal VPP which controls the word lines of the memory cells is generated using the VREFP signal as a power source and a reference signal. However, if the voltage level of the VREFP signal is increased to increase the speed of the semiconductor memory device, several problems occur. First, the voltage level of the boosted power supply signal VPP, which controls the word line of the chip, is increased above the required level such that an excessive voltage is applied to the wordline during normal operation. This becomes a more serious problem as the difference between the voltage levels of the two signals increases.
Second, when the voltage level of the VREFP signal increases, the boost voltage generator must operate at an excessive rate to maintain the voltage level of the boosted power supply signal VPP above the required level. This results in excessive current consumption.
Accordingly, a need remains for an improved technique for generating a boosted power supply signal for controlling a memory cell array in a semiconductor memory device.